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IRS2509SPbF
Figure 19: Negative V S transient SOA for IRS2509 @ VBS=15V
Even though the IRS2509 has been shown able to handle these large negative V S transient conditions, it is highly recommended that
the circuit designer always limit the negative V S transients as much as possible by careful PCB layout and component use.
PCB Layout Tips
Distance between high and low voltage components: It’s strongly recommended to place the components tied to the floating voltage
pins (V B and V S ) near the respective high voltage portions of the device. Please see the Case Outline information in this datasheet
for the details.
Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high voltage floating
side.
Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure 20). In order to
reduce the EM coupling and improve the power switch turn on/off performance, the gate drive loops must be reduced as much as
possible. Moreover, current can be injected inside the gate drive loop via the IGBT collector-to-gate parasitic capacitance. The
parasitic auto-inductance of the gate loop contributes to developing a voltage across the gate-emitter, thus increasing the possibility
of a self turn-on effect.
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